1. Field of the Invention
The present invention pertains to the field of microprocessor architecture and layout. More particularly, this invention relates to placing properly sized clock buffers in the proper location within a logic block to reduce clock skew.
2. Background
Components of an integrated circuit operate based on timing and pulsing of clock signals which provide a reference point or activation signal for circuit activity and processing. The clock signals also provide a timing or alignment reference which different circuits adopt when stepping through their respective processing tasks. It is important that the clocking signals be predictable and not delayed such that processing and execution by circuit components are accomplished in synchronization. Microprocessor integrated circuit devices utilize a system clock which provides timing and pulsing to drive the various elements and processing of the microprocessor.
It is vital to the operation of a microprocessor that the system clock be supplied uniformly to all components of the microprocessor with minimal clock skew. Clock skew refers to the variations in timing delays between a system clock and a clock signal reaching a component. Resistance within the clock line and capacitance on the clock line creates RC skews, a type of clock skew, as the clock signal propagates. Clock buffers can be used to deskew the clock signal, thus a system for automatically placing the proper clock buffers in the correct locations would be advantageous.
A similar problem is that of a minimum delay between latches. A minimum delay problem may arise when the signal from a source latch is input into a receiving latch. If the clock signal driving the receiving latch reaches the receiving latch after the signal from the source latch arrives, the receiving latch may latch the wrong data. Thus, a buffer may be inserted into the line between the two latches to create a delay such that the signal does not arrive prior to the clock signal.
Design techniques for microprocessors may include utilization of a large number of functional blocks in order to shorten the design cycle. The functional blocks consist of a varying number of cells and utilize clock buffers to prevent clock skew. As microprocessors use faster and faster clock speeds, variations in clock skew within the functional blocks becomes a major concern. The slower clock speeds used in older microprocessor technology were slow enough that the clock skew within the functional blocks could be either ignored or resolved easily. However, faster clock speeds require that the problem of clock skew be addressed more efficiently.
In addition, microprocessor development times have become shorter and shorter. Therefore, an automatic system for the designer to insert the properly sized clock buffer in the proper location would be advantageous.
Thus, it would be advantageous to automatically optimally insert the proper clock buffers into the functional blocks. The present invention offers such a solution.
An example prior art placement of clock buffers is shown in FIG. 1A. The clock buffers 110 may have been placed arbitrarily, or at the very least in a non-optimized manner. That is, the clock buffers 110 were not guaranteed to be placed close to the clock line and thereby reduce clock skew. Additionally, as shown, the latches 120 were not necessarily driven by the clock buffer 110 located closest to each latch 120.
Other prior art placements of clock buffers may have attempted to solve the clock skew problem by placing clock buffers close to the latches being driven, as shown in FIG. 1B. However, as is readily apparent in FIG. 1B, the placement of the clock buffers 110 is not optimized because the buffers 110 are not placed close to the clock line 100. The extra distance between the clock line 100 and the buffers 110 over narrower lines 115 cause additional RC skew, thus, the reduction of clock skew is not optimized.